A goal in sample-and-hold circuits is to facilitate high-frequency operation while providing low power consumption. Additionally, it is sometimes desirable to perform one or more mathematical functions on a signal or signals before the resultant signal is sampled and held. The mathematical function may be any combination of multiplication, division, addition or subtraction. Implementing the mathematical function or functions and the sample-and-hold functions separately is typically area and power inefficient. It may be, therefore, desirable to combine the various operations in an efficient way without sacrificing accuracy, speed or power.
One approach to combining these functions is to use a differential gain stage, which performs the mathematical function, to drive a sample-and-hold circuit comprising a CMOS switch and a storage device. A problem with this approach is that the CMOS switch tends to have injection into the storage device, which is level dependant. This level dependency generally degrades the performance of the sample-and-hold circuit. In addition, high speed designs will often preclude the clock from being at levels suitable for proper CMOS operation, because, for example, the voltage level will often be limited to decrease propagation time. In such circumstances, the use of a CMOS switch may be inappropriate because the voltage swing of the signal may not be adequate to turn the switch on and/or off.
Another approach is to use a differential gain stage to drive bipolar junction transistors acting as a switch for the storage device. The bipolar junction transistors often consist of diodes which level shift up and down during sample mode. A problem with this approach is that these switch designs are inefficient and consume power.
Still another approach consists of a differential gain stage having a buffer driver off the load, which directly drives the storage element. In hold mode, the load is directly pulled down while depriving current to the driver. A problem with this approach is that the circuitry required to pull down the load tends to slow the operation of the circuit. Operation at higher speeds typically requires loads with low resistance. Using loads with low resistance generally requires a larger current to pull the voltage of the load down sufficiently to enter hold mode. Thus, this approach requires high current levels for high speed operation. In addition, the voltage on the load may be influenced by variations in the input signal. These variations may propagate to the storage element and corrupt the stored signal.